The present invention relates generally to a semiconductor device and method of forming the same and, more specifically, to CMOS SiGe channel pFET and Si channel nFET devices.
For certain technology node device requirements, it may be necessary to use different channel materials on nFET and pFET devices. The channel materials may be grown using epitaxial growth techniques. In high-k/metal-gate technologies, silicon germanium (SiGe) may be used as the pFET channel material to assist in reaching a desired pFET metal-semiconductor workfunction, while maintaining a traditional silicon channel for the nFET devices. When using epitaxial growth for channel materials on a desired device, a hardmask material such as silicon dioxide (SiO2) or silicon nitride (SiN2) may be used to protect against growth of new channel material on the other devices. The hardmask material is then removed.
Nitride hardmasks are usually not used when growing silicon germanium (SiGe) channel materials. The etchant, such as hot phosphoric acid, used to remove the nitride hardmask also etches the silicon germanium (SiGe) material itself. Patterning of oxide hardmasks with common oxide etchants, such as hydrofluoric acid, also etches the shallow trench isolation (STI) oxide resulting in a different step-height (STI oxide height relative to channel silicon) between nFET and pFET devices. Different size STI divots (amount of STI oxide pulldown immediately next to the active silicon device) may also occur between nFET and pFET devices. Step-height differences and divot differences can create structural topography problems in downstream processing as well as electrical device issues, such as leakage, performance, active width and corner device. A large difference can exist between STI areas and active silicon areas in pFETs versus nFETs. This is all driven by the patterning of the hardmask layer used to protect the nFET device from receiving epitaxial growth. The size of the STI divots near the edge of the active silicon are drastically asymmetrical.